# Asynchronous dual-clock FIFO

## Run the simulation

With Icarus Verilog installed, run these commands from this folder.

```sh
iverilog -g2012 -Wall -s tb_async_fifo -o simulation rtl/async_fifo.sv tb/tb_async_fifo.sv
vvp simulation
```

## Integration notes

[RTL](rtl/async_fifo.sv) · [Testbench](tb/tb_async_fifo.sv)

Set `DATA_WIDTH` to the word width and `ADDR_WIDTH` to the address width. Both must be at least one. Capacity is exactly `2 ** ADDR_WIDTH` words.

A write is accepted on a rising `wr_clk` edge when `wr_en && !wr_full`. A read is accepted on a rising `rd_clk` edge when `rd_en && !rd_empty`. The accepted word appears in the registered `rd_data` with `rd_valid` after that read edge. Back-to-back reads can keep `rd_valid` high. Sample full only in the write domain and empty and valid only in the read domain. A common active-low reset flushes the FIFO, with synchronous release in each domain.

Binary pointers address dual-port storage. Registered Gray pointers cross through two synchronizer stages, and each domain generates its own full or empty flag. Flag release can lag remote activity by a few local clock cycles while the pointer propagates. Reset clears pointers and flags, and `rd_valid` qualifies the read data. [Clifford Cummings, asynchronous FIFO design](https://www.researchgate.net/profile/Clifford-Cummings/publication/252160343_Simulation_and_Synthesis_Techniques_for_Asynchronous_FIFO_Design/links/54bfe9720cf28eae4a66418a/Simulation-and-Synthesis-Techniques-for-Asynchronous-FIFO-Design.pdf)

For a specific target, review dual-port RAM inference and apply the device toolchain’s delay and skew constraints to both Gray-pointer crossings. Check those paths and the reset synchronizers in the target CDC and timing reports. The supplied checks cover RTL behavior and generic synthesis. Target-specific timing closure, metastability analysis, and physical hardware validation remain integration work. [AMD Vivado CDC constraints](https://docs.amd.com/r/en-US/ug903-vivado-using-constraints/Constraining-Asynchronous-Signals)