# AXI4-Lite register bank and SPI master

## Run the simulation

With Icarus Verilog installed, run these commands from this folder.

```sh
iverilog -g2012 -Wall -s tb_axil_spi -o simulation rtl/axil_spi.sv rtl/spi_master_mode0.sv tb/tb_axil_spi.sv
vvp simulation
```

## Integration notes

[AXI/register RTL](rtl/axil_spi.sv) · [SPI RTL](rtl/spi_master_mode0.sv) · [Testbench](tb/tb_axil_spi.sv)

The peripheral uses a 32-bit AXI4-Lite interface. Write address and write data are buffered independently, so either can arrive first. The interface allows one outstanding read and one outstanding write. Responses remain stable until accepted. Deassert `aresetn` synchronously to `aclk`. The register map uses aligned byte offsets from the peripheral base. Connect the address inputs to local offsets when mapping the block at a nonzero system address. Apply any access policy in the interconnect. [Arm AMBA AXI specification](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/IHI0022H_amba_axi_protocol_spec.pdf)

| Offset | Register | Access | Behavior |
| --- | --- | --- | --- |
| `0x00` | STATUS | Read, write-one-to-clear | Bit 0 is busy. Bit 1 latches completion. Write bit 1 in byte lane 0 to clear it. |
| `0x04` | DIVIDER | Read/write | Bits 15:0 give ACLK cycles per SPI half period. Reset value is 2. A write that would make the divider zero returns `SLVERR`. |
| `0x08` | TXDATA | Write | Writing byte lane 0 starts a frame using bits 7:0 and clears the previous completion. A start while busy returns `SLVERR`. |
| `0x0C` | RXDATA | Read | Bits 7:0 hold the byte received in the most recently completed frame. Reset value is zero. |

Byte strobes affect only the lanes implemented by each writable register. Unsupported addresses and access directions return `SLVERR`. An accepted divider change during a frame takes effect on the next frame.

The SPI engine transfers one eight-bit, MSB-first frame per start using active-low chip select and mode 0. It drives chip select and SCK from registers, presents MOSI before each rising edge, and captures MISO at the corresponding sampling event. SCK runs at `ACLK / (2 × DIVIDER)` during a frame. Chip select stays asserted for a half period after the final falling edge. Check the external device’s chip-select spacing and board-level I/O timing when integrating the peripheral. [Microchip SPI transfer modes](https://onlinedocs.microchip.com/oxy/GUID-DE09DA5A-1CBB-49A8-9DA0-B2EB94E57E56-en-US-11/GUID-67490DA2-F73A-42D5-889A-2AF016ADDFE3.html)