#include "axil_spi.h"

/* These accessors assume the board maps this range as ordered device memory.
 * Substitute board-support-package accessors where barriers or byte swapping
 * are required. A volatile access alone does not configure bus ordering.
 */
uint32_t bss_spi_read32(uintptr_t address)
{
    return *(const volatile uint32_t *)address;
}

void bss_spi_write32(uintptr_t address, uint32_t value)
{
    *(volatile uint32_t *)address = value;
}

/* Call from your board's startup code after assigning the peripheral base,
 * enabling its clock, and releasing reset. Connect MOSI to MISO for this test.
 * Returns 0 on success, 1 on setup/transfer failure, and 2 on a mismatch.
 */
int bss_spi_loopback_example(uintptr_t spi_base)
{
    const uint8_t tx = UINT8_C(0xA6);
    uint8_t rx = 0;

    if (bss_spi_set_divider(spi_base, 4) != BSS_SPI_OK ||
        bss_spi_transfer_byte(spi_base, tx, &rx, 1024) != BSS_SPI_OK) {
        return 1;
    }

    return rx == tx ? 0 : 2;
}