# Round-robin bus arbiter

## Run the simulation

With Icarus Verilog installed, run these commands from this folder.

```sh
iverilog -g2012 -Wall -s tb_round_robin_arbiter -o simulation rtl/round_robin_arbiter.sv tb/tb_round_robin_arbiter.sv
vvp simulation
```

## Integration notes

[RTL](rtl/round_robin_arbiter.sv) · [Testbench](tb/tb_round_robin_arbiter.sv)

Set `REQUESTERS` to the number of inputs, with a minimum of one. Each input holds its request and payload until its one-hot grant is accepted at a rising clock edge with `grant_valid && grant_ready`. Use the grant to select data in the surrounding bus logic.

The scan starts at the next priority index and wraps at the actual requester count. When the output stalls, the arbiter holds the selected grant. Priority advances only after an accepted grant. A continuously asserted request can be preceded by at most `REQUESTERS - 1` other accepted grants. Drive the active-low reset for at least one rising clock edge. The first priority after reset is requester zero.

The scan is a simple combinational implementation. For a large requester count or a tight clock budget, check the arbitration path after synthesis and placement.