RTL design and verification
Custom Verilog and SystemVerilog for datapaths, state machines, and bus interfaces. I can also verify existing RTL and integrate IP blocks.
RTL design & firmware
Custom digital logic, verification, and bare-metal C drivers for hardware startups, research labs, and individual FPGA developers.
What I can help with
Firmware drivers
Bare-metal C drivers and register abstraction headers for custom peripherals, built around your register map.
Who it’s for
Hardware startups
Add a custom RTL block to your prototype or integrate IP into an existing design.
Research labs
Implement an experimental architecture in RTL so your team can simulate and evaluate it.
Individual FPGA developers
Get help designing or verifying an RTL module for your own FPGA project.
Project pricing
I calculate fixed-price quotes using the estimated hours at $80 USD per hour. Each quote lists what I’ll deliver, how I’ll verify it, and the proposed delivery date.
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RTL review and debug
By estimated hours to complete
Review an existing RTL block or investigate a specific simulation issue.
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Custom RTL design
By estimated hours to complete
Design a self-contained RTL block with a defined interface and a self-checking testbench.
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Firmware drivers
By estimated hours to complete
Bare-metal C drivers and register abstraction headers for your peripheral.
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Larger projects
By milestone
I break larger projects into stages and quote a fixed price for each milestone based on the hours I estimate for that stage. Each milestone has its own deliverables and acceptance checks.
Team
Meet Jakub HammondHow to start a project
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Describe the project
In your first email, tell me what you’re building, what you have so far, and where you need help. Include the target FPGA or processor, relevant interfaces, and any delivery date you’re working toward, if known.
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Arrange to share sensitive files
Start with a nonconfidential summary. If I need source code, register maps, or other private materials to assess the work, we’ll agree on how to share them. See the Partner Confidentiality Policy.
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Agree on the scope and quote
I’ll follow up with any questions and send a fixed-price quote covering deliverables, verification checks, and a proposed delivery date. We’ll confirm those details by email before work begins.
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Keep decisions in one thread
Reply in the same email thread with feedback, decisions, or changes. When you send revised requirements or files, say what changed and which version to use. We’ll confirm any effect on price or timing before proceeding with the change.
Partner Confidentiality Policy
Big Sur Silicon keeps partner identities and project information confidential, from the first inquiry through project completion and afterward.
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What stays private
This includes who I work with, whether we are working together, and any nonpublic project information you share, such as specifications, RTL, testbenches, simulation results, and design files.
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How I use and share information
I use confidential information to evaluate your request and carry out the agreed work. I don’t share it with other clients, use it on another project, or publish your name, logo, or work without your written permission. I disclose information when required by law.
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Sharing sensitive files
Start with a brief, nonconfidential description. Before you send sensitive files, we can agree on how to transfer them and discuss any confidentiality agreement or access requirements.
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After the project
I continue to treat your information as confidential. We can agree in writing on which materials to return, retain, or delete at handoff.
Open to everyone
I welcome project inquiries from everyone. I apply the same criteria to each request, including the technical scope, verification requirements, and my capacity to deliver.
Tell me what you’re building
See how to start a project for what to include in your first email.
[email protected]