Hardware startups
Add a custom RTL block to your prototype or integrate IP into an existing design.
Custom RTL design
For hardware startups, research labs, and individual FPGA developers.
What I can help with
I design and verify custom Verilog and SystemVerilog modules, including datapaths, state machines, and bus interfaces. I can also help integrate existing IP blocks into your design.
I also write firmware drivers for custom peripherals, including bare-metal C driver code and register abstraction headers. I use your register map to define register offsets and bit fields and build functions to configure and operate the hardware without an operating system.
Browse RTL and firmware samplesWho it’s for
Research labs
Implement an experimental architecture in RTL so your team can simulate and evaluate it.
Individual FPGA developers
Get help designing or verifying an RTL module for your own FPGA project.
Partner Confidentiality Policy
Big Sur Silicon keeps partner identities and project information confidential, from the first inquiry through project completion and afterward.
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What stays private
This includes who I work with, whether we are working together, and any nonpublic project information you share, such as specifications, RTL, testbenches, simulation results, and design files.
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How I use and share information
I use confidential information to evaluate your request and carry out the agreed work. I don’t share it with other clients, use it on another project, or publish your name, logo, or work without your written permission. I disclose information when required by law.
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Sharing sensitive files
Start with a brief, nonconfidential description. Before you send sensitive files, we can agree on how to transfer them and discuss any confidentiality agreement or access requirements.
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After the project
I continue to treat your information as confidential. We can agree in writing on which materials to return, retain, or delete at handoff.
Open to everyone
I welcome project inquiries from everyone. I apply the same criteria to each request, including the technical scope, verification requirements, and my capacity to deliver.
Project pricing
I use a rate of $80 USD per hour to calculate fixed-price quotes based on the estimated work. Each quote lists what I’ll deliver, how I’ll verify it, and the proposed delivery date.
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RTL review and debug
From $350
Review an existing RTL block or investigate a specific simulation issue.
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Custom RTL design
From $750
Design a self-contained RTL block with a defined interface and a self-checking testbench.
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Firmware drivers
By scope
Bare-metal C drivers and register abstraction headers for your peripheral, quoted at the same estimating rate.
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Larger projects
By milestone
For subsystems, IP integration, or more extensive verification, each milestone has its own price, deliverables, and acceptance checks.
Team
Jakub Hammond
RTL Designer
Steps to Consult
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Describe the project
In your first email, tell me what you’re building, what you have so far, and where you need help. Include the target FPGA or processor, relevant interfaces, and any delivery date you’re working toward, if known.
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Arrange to share sensitive files
Start with a nonconfidential summary. If I need source code, register maps, or other private materials to assess the work, we’ll agree on how to share them. See the Partner Confidentiality Policy.
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Agree on the scope and quote
I’ll follow up with any questions and send a fixed-price quote covering deliverables, verification checks, and a proposed delivery date. We’ll confirm those details by email before work begins.
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Keep decisions in one thread
Reply in the same email thread with feedback, decisions, or changes. When you send revised requirements or files, say what changed and which version to use. We’ll confirm any effect on price or timing before proceeding with the change.
Tell me what you’re building
For help with your first email, see the consultation steps.
[email protected]