RTL and firmware samples.
Explore SystemVerilog designs and a bare-metal C SPI driver, with source files and tests you can run.
Round-robin bus arbiter
Rotates priority among a configurable number of requesters and holds the selected grant during backpressure.
AXI4-Lite register bank and SPI master
A 32-bit AXI4-Lite register bank controls an eight-bit, full-duplex SPI mode 0 engine. The peripheral uses both design files.
Asynchronous dual-clock FIFO
Transfers words between independent clocks using synchronized Gray-code pointers and local full and empty flags.
Bare-metal C SPI driver
Configures the clock and transfers a byte through the AXI4-Lite SPI master. Includes a register header, a loopback example, and a test that runs the C driver against the RTL in simulation.
Test the three RTL samples
Combine the rtl/ and tb/ files in one folder with the Makefile and follow the collection README.